Power system simulator — draw a single-line topology and run the studies
This canvas is built for a computer
Drawing a single-line diagram and wiring devices with the mouse is a desktop job. The workspace is three columns side by side — device library, canvas and parameter panels — and needs a wide screen. We deliberately did not squeeze it into a phone layout: a compressed canvas would draw and connect unreliably, so on a phone this page is review-only.
Copy the link below and open it in a desktop browser (1280 px wide or more). Note that saved schemes live in this browser, so opening the link on a computer starts a fresh canvas.
You can look around and pan, but wiring and editing on a phone are unreliable. Use a computer for real work.
Start with your first deviceThe canvas is empty. Three steps and you can run the engine.
- 1Put a source on the canvas
- 2Wire it up
- 3Run the engine
These three entries stay one click away, and Clear canvas is always on the canvas toolbar as well.
Nothing is sent to the engine until you press Run — the canvas itself computes no physics.
Right-click a node / link to trip or restore
About the design canvas (builder)
This page is the scheme entry point of the simulator and the single trigger of the design pipeline. Devices are dragged onto the canvas (grid, transformer, MV / LV switchgear, busbar, breaker, ATS, UPS, load, PV, storage, genset, wind) and linked, then one POST /api/design call returns the whole calculation set — design.sc, pf, lf, cableSchedule, selection, bom, econ, draw plus the design.study{} block. The canvas itself computes no physics: every number comes from the engine modules whose standards are named on their own pages (IEC 60909 for short circuit, GB 20052 for transformer loss and efficiency, and the parameter single source engines/params.js). The live single-line diagram, the design cards and the protection setting sheet all read the same engine response.
Everything downstream inherits what is entered here. The device types decide which studies exist at all, the ratings decide the withstand and loading verdicts, and the cable section / length / material typed on each link are the single source shared by short circuit, load flow, loss allocation and the cable schedule. Topology checks (unconnected node, dangling port, missing rating, illegal loop) run before anything is computed, so a wrong canvas is caught here instead of surfacing as an odd number three pages later. It is also the only place where a scheme is written down once and reused by every other page through the scheme library.
Input: nodes and edges (each edge carries lenM, section, material, cores), external conditions (Ssc, X/R, voltage level), the operating case (run.gridOperation) and the study switches (studyOptions) → chain: engines/params.js flattens the canvas into flatNodes / flatEdges and resolves every default (a missing length falls back to DEFAULT_LEN_M; an illegal value falls back to a safe default and raises a warnings[] entry) → the electrical layer order LAYER is rebuilt and ports and links are validated → computeDesign runs the pipeline in order: (1) short circuit per IEC 60909 equivalent voltage source including the fault-point line impedance, (2) load flow (Ybus with constant-power iteration), (3) transformer loss P0 + Pk×(S/Sn)² with GB 20052 typical values when the user gives none, (4) cable schedule and selection checks, (5) quantities, BOM and economics, then the optional study{} blocks → output: design.sc, design.pf, design.lf, design.cableSchedule, design.selection, design.bom, design.econ, design.draw and design.study.*. Linkage: changing a cable section changes four things at once — Zk drops so the fault current rises (device Icw and the cable thermal minimum section follow), the I²R term moves in the loss allocation, the voltage drop moves in the load flow, and the protection sensitivity moves with the minimum fault current. Changing the transformer Uk moves short circuit and load flow together, and changing an edge length moves both the short-circuit fault-point impedance and the load-flow branch impedance because both read the same edge.lenM — there is deliberately only one length in the data model.